Harshal Ramtekkar

San Jose, California, United States
Meta

San Jose State University

2010-2012
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About

- Accomplished RTL design engineer specializing in RTL/Logic design, ASIC frontend development, and IP integration.- Expertise in NOC Design with a focus on Custom Mesh Fabric Interconnect and automation for fabric generation.- Proficient in Spyglass for CDC/RDC/DFT, VC Static, SDC constraint check, and timing closure through Logic Synthesis.- Successful IP ownership, managing all activities for release, and collaborating effectively with stakeholders.- Skilled in Micro-Architecture and IP Design, ensuring smooth project execution and communication with management.- Extensive experience in customer engagement, conducting feature code reviews, defining verification/methodology requirements, and orchestrating IP releases for various protocols. Protocol: AMBA AXI/AHB/APB, USB 3.0/3.1/3.2, UCIe, IOSF-SB, DDR, I2C, UPF (Low power intent)

Harshal Ramtekkar In Short

Harshal Ramtekkar is an experienced ASIC Digital Design Engineer with 12.2 years of work experience. He is skilled in various programming languages such as Verilog, Asic, SystemVerilog, C, Modelsim, VHDL, CMO, and more. He has worked at Intel Corporation and Synopsys Inc, gaining expertise in SoC Design and Asic Digital Design. Harshal has also interned at Broadcom and worked as a Software Engineer at GE. He is proficient in Static Timing Analysis (STA), Synthesis, and RTL coding. Harshal is based in the United States.

Harshal Ramtekkar's Professional Milestones

  • Graduate Intern (2011-07-01~2011-11-01): Assisted in organizing business events and contributed to strategic decision-making.
  • Teaching Assistant (2011-08-01~2012-05-01): Provided essential support to educators, contributing to improving their overall learning experience.
  • Senior ASIC Digital Design Engineer (2017-05-01~): Developing cutting-edge digital solutions, revolutionizing industries and driving innovation in the field of design.
  • Intern IC Design (2012-04-01~2012-12-01): Designing advanced design concepts to enhance user experience and drive business growth.
  • SOC Design Engineer (2021-02-01~): Optimized computer system efficiency through innovative web design capabilities and optimized functionality.
  • ASIC Digital Design Engineer II (2013-04-01~2017-05-01): Improving systems to meet tight deadlines and ensure seamless integration of the latest technologies.

Harshal Ramtekkar's Emails and Phone Numbers

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Work Experience

Meta

Menlo Park,California,United States

Software Development

112164
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Intel Corporation

Santa Clara,California,United States

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Synopsys Inc

Sunnyvale,California,United States

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Broadcom

San Jose,California,United States

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San Jose State University

San Jose,California,United States

Networksound

United States

Education

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Skill

Verilog

Asic

Systemverilog

C

Modelsim

Vhdl

Cmos

Functional Verification

Perl Script

Fpga

Integrated Circuit Design

System Verilog

I2c

Eda

Rtl Design

Amba Ahb

Shell Scripting

Jenkins

Certification

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Frequently asked questions

What is Harshal Ramtekkar's email address?

We found 4 Harshal Ramtekkar's email addresses

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We found 3 Harshal Ramtekkar's phone numbers

Which social media profiles does Harshal Ramtekkar have?

Harshal Ramtekkar's social media include: Linkedin, 

What company does Harshal Ramtekkar work for?

Harshal Ramtekkar works for Meta

What is Harshal Ramtekkar's role in Meta?

Harshal Ramtekkar's role in Meta is ASIC Design | NOC Design | IP Owner | Digital Front End | Integration | Automation

Which industry does Harshal Ramtekkar work in?
Harshal Ramtekkar works in the industry of Software Development
Who are Harshal Ramtekkar's colleagues?
Harshal Ramtekkar's colleagues are Carlos Mario Danger Corral,imran fokir,Umar Mehar
What is Harshal Ramtekkar's latest job experience?

Harshal Ramtekkar's latest job experience is ASIC Design | NOC Design | IP Owner | Digital Front End | Integration | Automation at Meta

What is Harshal Ramtekkar's latest education?

Harshal Ramtekkar's latest education in San Jose State University

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Harshal Ramtekkar is an experienced ASIC Digital Design Engineer with 12.2 years of work experience. He is skilled in various programming languages such as Verilog, Asic, SystemVerilog, C, Modelsim, VHDL, CMO, and more. He has worked at Intel Corporation and Synopsys Inc, gaining expertise in SoC Design and Asic Digital Design. Harshal has also interned at Broadcom and worked as a Software Engineer at GE. He is proficient in Static Timing Analysis (STA), Synthesis, and RTL coding. Harshal is based in the United States.
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