Marvell Technology>   Lenin Patra
Lenin Patra
Lenin Patra is a seasoned semiconductor executive with over 20 years of experience in the field. He has a strong background in analog, debugging, hardware architecture, testing, and ethernet. Lenin has a proven track record of delivering Networking products to top-tier Data Center and Enterprise customers. He has played a key role in joint planning and executing competitive products. Lenin has also worked as a Technology Chief Product Architect for Marvell's High-Speed Interconnect PHY product portfolios. He has expertise in developing AI HW accelerator platforms for deep learning and ML. .Read More

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About Lenin Patra

Seasoned semiconductor executive with proven track record of defining, architecting and delivering Networking products to top tier Data Center and Enterprise customers. Key Product leader involved in joint planning with various business units and operations for efficient development and execution of competitive products. Involved in strategic planning combining elements of product architecture, IP leverage, resource allocation, cost analysis to define the world class profitable PHY products. Technology --> Chief Product Architect for Marvell's High-Speed Interconnect PHY product portfolios (100G/200G/400G/800G based PHY integrated with MACSec security and IEEE-1588 and 802.1 AS rev based PTP engine capable of meeting Class C accuracy for 5G network) Leading the Next Gen 1.6T/3.2T chiplet architecture with mainstream 112G SerDes, capable of driving backplane as well as capable of driving Single Mode Fiber optics and 112G XSR, BoW based Die to Die interface for integration with Next Gen ASICs. Spearheading the Next Gen SerDes strategy (112G/224G/ PCIE-GEN-6) to drive the Silicon Photonics based Optical Engine for (CPO) Co-packaged Optics application in advanced process node -i.e. – TSMC -5nm, 7nm. Leading the product definition for Enterprise Multi-Gig Copper PHY (10G/5G/2.5G Base-T Copper PHY) for borderless enterprise networking And Next Gen Automotive PHY (1000BT1, 2.5G/5G/10G base-T1 PHY based on IEEE 802.3 ch) and upcoming 25G-T1 PHY in definition stage to address 802.3 cy Link segments). Expertise in developing the AI HW accelerator platforms for deep learning and ML. Execution --> 15 + Years of engineering excellence in execution of building complicated Networking, Enterprise and Automotive Products with speed ranging from 1G to 800G (8 X 100G PAM-4) for data center, enterprise and Automotive Applications in several process nodes - from 0.13um to 16nm/12nm/7nm/5nm FF process. Multiple Patents holder in High speed Networking communication fields. People Skill --> I thoroughly enjoy bringing the best out of engineering Team in crunch situation. Enjoy fostering collaboration between diverse teams of capable people. I facilitate decision making within disparate teams by articulating the challenges across disciplines and finding mutually excellent solutions. .Read More

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