Badrinarayan Parthasarathy
Design Verification@ Microsoft
Sammamish, Washington, United States
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Badrinarayan Parthasarathy is a highly skilled professional with 12.5 years of experience in systemverilog, verilog, vhdl, c, asic, uvm, fpga, python, test planning, debugging, c++, functional verification, computer architecture, arm architecture, security, field programmable gate arrays, synopsys tools, sas, sata, pcie, register access layer, functional coverage, silicon validation, axi, regression testing, fimware functional model, intel pipe4, i2c, verdi, alias, fab
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Emails and Phone Numbers

@microsoft.com
@qualcomm.com
@gmail.com
@gmail.com
+1 425895****
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About

~ What gets measured, gets done ~

Work Experience

1 Microsoft Way, Redmond, Washington, 98052, US

Software Development

225512
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Badrinarayan Parthasarathy's Professional Milestones

  • Design Verification (2019-06-01~): Streamlined design verification processes to ensure accurate and efficient design inspections.
  • ASIC Verification (2012-06-01~2014-08-01): Developed and implemented effective verification strategies, enhancing accuracy and efficiency in the ASS certification process.
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