Beatriz Olleta

Currently I am on a more technical demanding position; modelling of analog building blocks using systemverilog; creating and debugging IC netlist to be used on the UVM driven environment; as well as coordinating efforts and strategies. As always I try to close the gap between digital and analog. On my last 4 years at ams OSRAM I worked mostly as Design Verification Lead and Requirement Engineer of multi-chip, multi-technologies systems including microprocessors (ARM M0, M4) and Software. As DV lead I was leading a team of up to 20 DV Engineers per project. In this role I defined DV strategy, created work-flow, managed priorities, tracked progress, reported to management, reviewed results and coordinated communication between DV and Design. Since my background is on the Analog Design when needed I had also done some DV on the mixed signal using cadence ams tools (Spectre + Xcelium) using directed testcases in systemVerilog On my first years at ams AG I worked as Analog Designer for Sensors interfaces taking different roles according to the project needs. I worked as block designer, Technical Project lead and as validation and test support from design. Worked as Lead Designer of several different projects while on Allegro Microsystems: worked with System Engineer and Marketing to develop the datasheet and test plan, supervised the Layout Engineers, helped Product Engineer on test plan and oversaw the part until release to production; including microprobing, silicon evaluation and debugging of silicon. Also worked as part of a team of designers for other projects developed both in Argentina and in USA. In these projects I was in charge of several blocks (regulators, DACs, digital control logic, amplifiers) design and layout supervision.