Bhargava Narumanchi

Previously at Cavium, I have been involved in designing, developing and upgrading various functional blocks in OcteonTX, OcteonTX2 and Fusion line of ASICs where I have developed proficiency in various aspects of ASIC design flow such as micro-architecture modeling, RTL design, System Verilog DV, gate-level simulations, clock domain crossing checks.Building on that experience, I am currently working as an SOC engineer and learning the intricacies of developing complex, low power chips with multiple clock domains, reset domains, power domains with tight area restrictions.Additionally, my experience at NC state includes exposure to CPU micro architecture from pipelined processors to out of order super scalar processors. I have had the experience of modeling and evaluating structures such as dynamic schedulers and multi-level caches for SMPs.