Bhoomika Venugopal

I am a passionate Electrical Engineer with a Master's degree from the State University of New York at Buffalo. I have worked on projects in the Computer Architecture, Digital Design and CMOS VLSI domains. I am looking for full time opportunities in RTL / ASIC Design and Verification, Computer Architecture fields. My skills include: Programming: C, C++, Verilog; Scripting: Python, Perl, Shell; Verification: System Verilog, Assertions, UVM. Software Tools: Synopsys VCS, Cadence (Virtuoso, NC-Sim, RTL Compiler, Encounter RTL to GDS), Xilinx, Aldec, Matlab. Protocols/Methodologies: PCIe, SPI, Clock Tree Synthesis, Static Timing Analysis. Environment: Linux, Windows, Mac OS; Version Control: GitHub, CVS. I can be reached either through my LinkedIn profile or by email at [email protected].