Chaitanya Ummadisetty

-Experience in designing digital integrated circuits, ASIC design methodology, static timing analysis, clock tree synthesis, floor planning, place and route, delay and power analysis. -Experience in Verilog, System Verilog and Constrained random verification. -Strong background in Digital Circuit/RTL Design, Computer Architecture and Verification methodologies (SV, DPI, UVM). Core Competencies: -RTL Design & Verification. -Physical/Circuit Design & Physical Verification. -ASIC Design Flow (RTL to GDSII using Cadence Encounter), Static Timing Analysis using Synopsys Primetime. -Memory Design - SRAM, Register file Technical Skills: --CAD/EDA tools: Cadence Virtuoso, Encounter (P&R/APR), Primetime (STA), RTL Compiler, HSPICE, MATLAB Simulink. --Simulation & Verification Tools : ModelSim, Xilinx IDE, Riviera-PRO, Active HDL. --Languages: C, Verilog HDL, C++ (Object Oriented Programming), System Verilog (SVA, SVTB, SVDPI), UVM, Perl, Python (beginner) and bash Scripting. --Operating Systems: UNIX, Linux (Ubuntu) and Windows. Course Work: VLSI Design, Hardware Design and Verification Languages, Computer Architecture-I, Digital Systems and Circuits, Analog Integrated Circuits, System level Design for Multicore Architectures, Semi-Conductor Memory Technologies & systems.