Haviesh Kosuru

 Worked as a Design Intern.  Experience in writing Verilog, VHDL, System Verilog, RTL coding for high-level Logic Synthesis and Digital Signal Processing.  Proficiency in C, C++, Java Programming languages.  Fluent in Tcl, Perl, Python, Ruby and Shell scripting languages.  Experience in writing UPF/CPF for low power Design, Power Management Techniques.  Strong Experience in Advance Static and Formal Verification Techniques and tools like VCS, Modelsim, AMS verification, DFT.  Strong Experience in RTL power estimation & optimization, STA, and timing closure.  Strong Experience with EDA tools – Cadence Design Tools, Synopsys Design Compiler, Primetime, IC Compiler, Cadence Encounter, RTL Compiler, Conformal LEC.  Working experience with other tools like Matlab, LabVIEW, and Altera Quartus Prime  Proficiency in MS Office, Unix, and Linux operating systems.