Hirokazu Ezawa

My original expertise is in development of thin film metallization process, including sputtering, metal-CVD, electroplating and their related process integration for ULSI devices. I have a nearly 30 years experience to work for the development of gate salicide process, W contact plug formation, multilevel interconnection process, together with reduction of chip-package-interaction for lead-free solder bumping on low-k BEOL. Not only R&D, I had also a lot of opportunities to work in different mass production fabs to locate new production lines and, as newly developed products moved into mass production phase, I used to collaborate with fab engineers, together with engineers from equipment companies, on improvement of product yield, productivity and reliability. I organized a development team and put TSV into WLP for CMOS image sensor, what is called Chip Scale Camera Module, which has been the world first successful mass production of TSV process. Regarding 3D integration, I had been in charge of process development of mid-end technology including micro-bumping, fine-pitch Cu redistribution wiring, TSV multi die stacking, fan-out wafer level packaging to realize power efficient LSI devices with leading-edge CMOS logic stacked on wide I/O DRAM and TSV stacked flash memory module. My job contract with Toshiba Memory Corp. expired Sep. in 2019 at mandatory age limit. Now, I am giving a lecture on solid state physics one day a week at Kanagawa Institute of Technology. My current interests lie in development of fan-out panel level packaging, novel interconnect materials, hydrogen fuel cell carriers and a specific low power LSI devices.