Hsiu-Ting (Martin) Hsieh
silicon validation engineer at nvidia@ NVIDIA
San Jose, California, United States
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Hsiu-Ting (Martin) Hsieh is a highly skilled professional with 15.1 years of experience in VLSI design and post-silicon debugging. He has expertise in Matlab, C++, Cadence Virtuoso, Verilog, Perl, VLSI, XML, computer vision, C, electronics, debugging, Python, VHDL, and testing. Based in Taiwan, Hsiu-Ting (Martin) Hsieh has worked at NVIDIA as a Senior Silicon Validation Engineer and at Broadcom as a Hardware Engineering Intern. He also has experience as a Graduate Student at the University of Michigan and as a Teaching Assistant.
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Emails and Phone Numbers

@nvidia.com
@yahoo.com.tw
+1 408486****
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About

* Experience in VLSI design, and post-silicon debugging especially on memory validation * Extensive teamwork experience

Work Experience

2701 San Tomas Expressway, Santa Clara, CA, 95050, US

Computer Hardware Manufacturing

29043
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Hsiu-Ting (Martin) Hsieh's Professional Milestones

  • Hardware Engineering Intern (2012-08-01~2012-12-01): Contributed to the successful production of a highly efficient hardware system, contributing to the development of new hardware products.
  • Graduate Student (2011-09-01~2013-04-01): Graduated with honors, equipped with knowledge and abilities to excel in the field.
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Education

University of Michigan
University of Michigan

Electrical Engineering: Systems

1293840000-1356998400
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