JAYA PATEL
Physical Design Engineer@ Cadence Design Systems
Ahmadabad, Gujarat, India
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JAYA PATEL is a Physical Design Engineer with 5.8 years of experience in the semiconductor industry. Based in India, she has expertise in PnR, STA, LEC, ECO, and timing closure. She has worked at eInfochips (An Arrow Company) in San Jose, California, as a Physical Design Engineer and Trainee Engineer. She also has experience as a Project Intern at JK Lakshmi Cement Ltd. and Cadence Design Systems. JAYA PATEL is skilled in block-level PnR, STA, and PV, and has a strong background in EDA tools.
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Emails and Phone Numbers

@einfochips.com
@cadence.com
+1 408496****
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About

- Physical Design Engineer competent in PnR, STA, LEC, ECO and timing closure with 2.7 years of experience in the semiconductor industry. - Efficiently handled block-level PnR, STA and PV. --- EDA Tools worked --- ICC2, Innovus, PrimeTime,StarRC Conformal LEC, Formality Calibre, Voltus

Work Experience

2655 Seely Avenue, San Jose, California, 95134, US

Software Development

9598
Phone
+1 4089431234
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JAYA PATEL's Professional Milestones

  • Physical Design Engineer (2019-01-01~): Designing cutting-edge physical solutions to meet the evolving needs of diverse industry audiences.
  • Trainee Enginner (2018-07-01~): Inspiring and contributing to the development of an engineering team, delivering exceptional technical skills and skills training.
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Education

Nirma University, Ahmedabad, Gujarat, India
Nirma University, Ahmedabad, Gujarat, India2014-2018