Jeff Chen

Self-motivated and skilled at semiconductor new product introduction, including RF and SoC mixed-signal devices. Lead PCB design, test program development and debug, burn-in board design, silicon debug, and silicon characterization across PVT. Engage cross-functional team meetings to drive DFT to achieve better test coverage and test time reduction. Track record of providing solutions to RMA cases to reduce DPPM, improve yields, and deliver seamless test solutions for mass production.ATE Tester Platforms: Teradyne Catalyst, iFlex, UltraflexSoftware Skills: C/C++, VB/VBA/VBT, Microsoft Office, Python and Basic Perl.OS Platforms: Windows (XP, Vista, 7), Unix (Solaris, SunOS)Tools: Cadence Allegro Schematics Capture, Orcad PCB Layout, Syntricty, DataPower, SEDANADevice Types: SoC, Mixed Signal, GPS, Bluetooth, Wifi, Power Amplifier, LDOs, DCDC ConvertersLab Equiment: Oscilloscope, Spectrum Analyzer, Network Analyzer, Power Meter, DMMHandler/Prober Types: NS6040, NS7000, OPUS2, TEL12 Additional Skills- Design HTOL/HAST to support reliability qualification- Understanding DFT:Boundary Scan(JTAG), Scan ATPG and Memory Testing.