Kedar Bhatt
Circuit Design Engineer@ Intel Corporation
Austin, Texas, United States
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Kedar Bhatt is a highly skilled CPU Circuit designer at Intel Corporation with 11.2 years of experience. He is proficient in various programming languages such as Verilog, MATLAB, C, VLSI, C++, and Cadence Virtuoso. Kedar has a strong background in analog circuit design, characterization, and analog circuit design. He has also worked as a Graduate Technical Intern at Intel Corporation and as a Research Assistant. Kedar is based in the United States and has a passion for semiconductor manufacturing and electronics.
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@gmail.com
@intel.com
@intc.com
+1 049300****
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About

Kedar Bhatt. CPU Circuit designer at Intel Corporation. Location: Austin ... Graduate Technical Intern · Intel Corporation. July 2014 ... August 2012 – July 2013 (1 year)Mumbai Area, India. Developed ... Gujarati ... N.R. High School, Ahmedabad...

Work Experience

Robert Noyce Building, Santa Clara, California, 95052, US

Semiconductor Manufacturing

123387
Phone
+1 4087658080
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Kedar Bhatt's Professional Milestones

  • Circuit Design Engineer (2014-07-01~2014-12-01): Graduated with honors, equipped with tools and expertise for a successful career in technical engineering.
  • Research Assistant (2012-08-01~2013-07-01): Conducted thorough research in key scientific issues, contributing valuable insights to the field.