Lakshmanaswamy Arumugam

 A clear communicator to lead a Team and also able to create an environment to win  Responsible for Subsystem development for SoC deliveries  Good Knowledge in IPsec, MACsec Protocols  Good Knowledge in Peripherals and Memory controllers (ONFI-NAND,DDR CTRL/PHY,SPI-NOR/NAND,SRAM,SD,SDIO,MMC,UART,TIMER,)  Good Knowledge in AXI, AHB, APB, PCI, Prime cell DMA controller(PL.080) protocols  Experience in Verilog, VHDL HDLs  Knowledge in System Verilog  Experience in MIPS CPU Model Virtual platform integration and C based Subsystem Integration tests generation for SoC platforms  Experience in Microarchitecture and RTL description of various designs  Experience in Atrenta LINT , Spyglass and CDC tool  Experience with Constraints Bringup Block and SoC Level , STA and Timing Signoff (Cadence Tempus ,Synopsys PT)  Experience in Synthesis for Altera and Xilinx FPGA's  Experience in Test Suite generations and regression testing  Experience in IPXACT, GenBuild, Gensim integration tools  Knowledge in scripting languages Perl and Python