Laxman Arram
DFT Architect and Lead at Intel Corporation, India@ Intel Corporation
San Francisco, California, United States
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Laxman Arram is a Senior DFT Engineer with 23.8 years of experience in the field. He has expertise in dft, asic, verilog, atpg, and debugging. Based in San Francisco, California, Laxman has a strong understanding of the complete DFT cycle for SoC/ASICs. He is skilled in trade-off analysis, validation/simulation, and ATE pattern hand-off. Laxman has hands-on experience in Verilog/VHDL RTL Coding, Synthesis, STA, Formal Verification and Simulations, Post-Silicon Pattern bringup and Debug. He is also a mentor and managing team.
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+1 049300****
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About

Senior DFT Engineer with in-depth knowledge and hands-on experience on the complete DFT cycle for SoC/ASICs - Definition of complete DFT architecture with required trade-off analysis, implementation, validation/simulation and ATE pattern hand-off - Hands-on design, implementation and validation/simulation of Test Mode control/logic blocks. - Hands-on experience in Verilog/VHDL RTL Coding, Synthesis, STA, Formal Verification and Simulations - Post-Silicon Pattern bringup and Debug - Mentoring and managing team

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Work Experience

Robert Noyce Building, Santa Clara, California, 95052, US

Semiconductor Manufacturing

123387
Phone
+1 0493001400
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Laxman Arram's Professional Milestones

  • Contract - Sr. Dft Engineer For Wlan Group (2008-03-01~2009-02-01): Successfully completed CAD projects, ensuring efficient production and client satisfaction.
  • Senior Member Techincal Staff (2006-01-01~2007-10-01): Successfully supported departmental projects, demonstrating exceptional leadership and collaboration within the tech industry.
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Education

PSG College of Technology
PSG College of Technology

Communication Systems

1999-2001
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