Masami Hane

1987: Graduated Keio University, Master of Science and Technologies.1987-1993: Engaged in advanced TCAD technology development, especially process/device simulation model research and development in NEC Corporation. Microelectronics Research Laboratories.1993-1994: Visiting Scholoar in Center for Integrated Systems, Stanford University. engaged in Etching/Deposition process simulation modeling project "SPEEDIE" of Prof. K. Saraswat. 1994-1997: Associated Manager of advanced TCAD process/device modeling group, in Silicon System Devices Research Laboratory, NEC Corporation.1996-1999: SELETE 3D Process/Device Simulation tool developemnet project. 1997-2007: Manager of advanced CMOS device research group, in Silicon System Devices Research Laboratory, NEC Corporation. Engaged in early development of 45nm-32nm CMOS platform devices. 2003: Ph.D. dissertation approved by Keio University, in Electrical Engineering.2008-2011: In IBM preT0 CMOS device research project, as an project manager of Renesas Elecronics America, working in Albany, NY. Engaged in 20nm-14nm bulk CMOS devices early development. 2011-2013t: Department head, LSI device research laboratory, Renesas Electronics Corporation.----------------- International Conference Activity --------------1998-present : IEEE Electron Devices Society, AdCom of TCAD Program Chair of 2005 SISPAD (International conference of Simulation of Semiconductor Processes and Devices The conference is the leading forum for Technology Computer-Aided Design (TCAD) 2001-2002 IEDM (International Electron Devices Meeting) program committee of Modeling/Simulation 2006-2007 IEDM program commitee of Modeling/Simulation2007 SSDM Area3 Chair 2008-2009 IEDM Asian arrangement chair2010 IEDM Publication Chair2012-2013 VLSI symposium, Technology Short Course Organizers/Chairs