software verification and validation engineer certified safe5 scrum master@ Roche
San Francisco, California, United States
Neha Shah
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San Jose State University
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FlashIntel GPTNeha Shah is an experienced MSE with 8.6 years of work experience in Verilog and SystemVerilog verification architecture. She has expertise in functional verification, test case development, scripting, and regression using Perl, Shell, and Makefile. Neha is currently seeking a position as an ASIC/SoC Verification Engineer. She specializes in languages such as SystemVerilog, Verilog, C, and has knowledge of tools like MTI, Verdi, VCS, SimVision, VSIM & URG, Aldec Riviera Pro, Perforce, NC-Verilog, Virtuoso-Cadence, IC Compiler, Design Compiler, and Scripting. Neha
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MSE with experience in Verilog and SystemVerilog verification Architecture, Functional Verification, Test case development, Scripting and Regression using Perl, Shell and Makefile, Functional Coverage, SystemVerilog UVM constraint random testbench, Looking for ASIC/SoC Verification Engineer position. Specialties: * Languages: SystemVerilog, Verilog, C. * Methodology: SystemVerilog UVM. * Tools: MTI, Verdi, VCS, SimVision, VSIM & URG (coverage tool), Aldec Riviera Pro, Perforce, NC-Verilog, Virtuoso-Cadence, IC Compiler, Design Compiler. * Scripting: Perl, Shell, Makefile. . Protocol: AMBA AXI * Operating System Environments: Linux, UNIX, Windows.
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software verification and validation engineer certified safe5 scrum master
Biotechnology Research
Neha Shah's Professional Milestones
- Software Quality Engineer (2015-03-01~2018-03-01): Implementing robust quality control measures to ensure consistent product quality and customer satisfaction.
- software verification and validation engineer certified safe5 scrum master (2022-04-01~): Developed and executed innovative processes for improving software quality and efficiency.
Education
Engineering,
Master Of Science,
Masters
2007-2010Certification
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