Nimish Shah

I am a PhD researcher designing cohesive hardware-software solutions for challenging computational problems. I have designed processors and compilers for efficient parallel execution of irregular and sparse computational problems arising in machine learning and linear algebra. I have hands-on experience with the complete digital ASIC flow and tape-outs. Key expertise: • Parallel digital systems and computer architectures • Digital IC design and verification, with ASIC tape-out experience • Processors for machine learning, sparse linear algebra, and graph analytics • Customized computer arithmetic representations and hardware • Low-power VLSI techniques • Scheduling and mapping for optimized parallel execution • FPGA prototyping, PCB designing, silicon testing and bring-up • Combinatorial optimization algorithms and tools • Embedded systems hardware and software A proven track record of excellent scientific contributions through publications in ISSCC, JSSC, NeurIPS, DAC, DATE, ITPDS, ITNNLS, etc. Google scholar profile: scholar.google.com/citations?user=oeaCGYUAAAAJ