Pallav Rana
uefi ddr firmware engineer at intel corporation@ Intel Corporation
Bengaluru, Karnataka, India
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Pallav Rana is a DDR Memory Reference Firmware Developer with 9.2 years of experience. He specializes in LPDDR Memory Subsystem initialization and physical interface calibration routines. Pallav is responsible for developing pre/post silicon DDR memory training algorithms and features to ensure optimal functioning of DRAM and Memory Subsystem. He has worked on Intel Silicon products supporting LPDDR memory interface and is skilled in Python, C programming, Firmware Development, Intel Architecture, and Public Speaking. Pallav has worked at Intel Corporation in Santa Clara, California as a Silicon Firmware Engineer and an Intern.
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Emails and Phone Numbers

@intel.com
@rediffmail.com
@intc.com
+91 049300****
+91 408765****
+1 408765****
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About

DDR Memory Reference Firmware Developer -> Specializing in LPDDR Memory Subsystem initialization and Physical Interface calibration routines -> Responsible for developing Pre/Post Silicon DDR memory training algorithms and features to ensure optimal functioning of DRAM and Memory Subsystem -> Worked on Intel Silicon products supporting LPDDR memory interface -> Skilled in Python, C programming, Firmware Development, Intel Architecture , Public Speaking. Strong engineering professional

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Work Experience

Robert Noyce Building, Santa Clara, California, 95052, US

Semiconductor Manufacturing

123387
Phone
+1 4087658080
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Pallav Rana's Professional Milestones

  • Trainee (2014-07-01~2015-05-01): Graduated with honors, equipped with an extensive technical proficiency and dedication to daily life.
  • Intern (2017-05-01~2018-05-01): Mastered the art of designing and implementing software, gaining invaluable hands-on experience in various areas of work.
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Education

Gujarat Technological University (GTU)
Gujarat Technological University (GTU)

Electronics And Communications Engineering

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