Senior Principal Application Engineer@ Cadence Design Systems
Baltimore, Maryland, United States
Patrick Santavenere
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The Johns Hopkins University
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FlashIntel GPTPatrick Santavenere is a highly experienced Microelectronics Engineer with 38.9 years of work experience. He specializes in front-end ASIC and SoC design, synthesis, static timing analysis, and design-for-test. Patrick has a strong background in technical and sales support in the electronic design automation industry. He has worked at Cadence Design Systems and Atmel Corporation, where he held senior positions as a Senior Principal Application Engineer and Senior Individual Contributor. Patrick also has experience as a Senior Applications Consultant and Senior Design Engineer at Synopsys Inc.
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About
Microelectronics Engineer with extensive experience specializing in front-end ASIC and SoC design, synthesis, static timing analysis and design-for-test. Considerable experience in technical and sales support in the electronic design automation industry. Design Software: Cadence: Genus, Modus, Conformal LEC, Xcelium Synopsys: Design Compiler, DFT Compiler, PrimeTime, TetraMax, Formality; Atrenta: Spyglass OS/Scripting: Unix/Linux, SunOS, Windows, MacOS, csh, tcl Others: Verilog RTL
Work Experience
Senior Principal Application Engineer
Software Development
Patrick Santavenere's Professional Milestones
- Engineer (1985-01-01~1991-01-01): Empowered and empowered teams to excel in engineering projects, driving success and fostering team collaboration.
- Senior Principal Application Engineer (2013-03-01~): Implementing cutting-edge technology solutions to enhance software performance and efficiency.
Education
Electrical Engineering,
Master Of Science,
Masters,
Bachelors,
Bachelor Of Science In Electrical Engineering
Skill
Verilog
Asic
Static Timing Analysis
Eda
Logic Synthesis
Tcl
Simulations
Synopsys Tools
Formal Verification
Front End
Testing
Primetime
Hardware Architecture
Rtl Design
Atpg
Customer Support
Electrical Engineering
Digital Circuit Design
Arm
Rtl
Integrated Circuit Design
Functional Verification
Front End Hardware Design
Verilog Rtl
Gate Leve And Rtl Simulation
Design For Test
Applications Engineer
Soc
Certification
Colleagues
Lip-Bu Tan
President | Chief Executive Officer
Jim Cowie
Advisor To The Chief Executive Officer
Matthew Noseworthy
Founder
Madhuparna Datta
VFSA Expert | Founder
Rosemary Nwosu-Ihueze
founder @kemdi attire | google csrmp 2021 | gem fellow | software developer | ux designer
Other Named Patrick Santavenere
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Patrick Santavenere works for Cadence Design Systems
Patrick Santavenere's role in Cadence Design Systems is Senior Principal Application Engineer
Patrick Santavenere works in the industry of Software Development
Patrick Santavenere's colleagues are Lip-Bu Tan,Jim Cowie,Matthew Noseworthy
Patrick Santavenere's latest job experience is Senior Principal Application Engineer at Cadence Design Systems
Patrick Santavenere's latest education in The Johns Hopkins University
