Prajakta Upadhye

Total Work Experience of 3.8 years. Presently, Working onshore as Senior Engineer for 2.8years, as Contractor. After M Tech degree from Manipal University Jaipur with CGPA 9.04, I have since completed PGD-VLSI (Grade A) from CDAC ACTS and Advance VLSI course from Maven Silicon. Having good experience in writing Testcases and assertions to verify the functionality of the design. Worked in developing the testbench environment in Verilog/ SystemVerilog/UVM. Worked in various domains of verification: formal verification, GLS Verification, Block level Verification, and SOC Verification. Having good knowledge of coverage analysis and verification methodologies. I have worked on industry-standard verification flow from concept to signoff.