Raju Agarwal

March 2023 ~ Present :- Started working on Logic Synthesis and APR with qor analysis taking the design through EMIR , (LV verification)DRC checks , FEV , STA and other Sign-off checks. Experience in Static Timing Analysis signoff with exception coding for full-chip level, tape-out signoff requirements & corresponding automation. Experience in extraction of design parameters, QoR metrics, and analyzing the STA violations across corners. Experience in ECO generation , what-if analysis for timing convergence across corners. Experience in STA tools (such as Primetime) and methodologies for timing closure with a good understanding of OCV, derates , guard-band , noise, cross-talk, and cross-corner variation. Experience in high frequency custom clock building from PLL to clock divider minimizing skew and uncertainty. Experience in scripting languages such as Tcl, Perl , C-shell .