Saurabh Jain
iisc | asic ip@ NXP Semiconductors
Noida, Uttar Pradesh, India
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Saurabh Jain is an experienced IP RTL Design Engineer with 11.7 years of work experience in the semiconductors industry. He is skilled in Microarchitecture, RTL coding, Verilog, and has a strong understanding of SystemVerilog, UVM, and Shell Scripting. Saurabh has worked at NXP Semiconductors in the Netherlands as a Technical Manager and Ip Lead Engineer, and at STMicroelectronics in Switzerland as a Technical Lead. He also has experience as an Asic Design Engineer at Marvell Technology in the United States. Saurabh holds a Master of Technology degree in Electronic design from the Indian Institute of Science.
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@nxp.com
@gmail.com
@st.com
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+31 402729****
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About

Experienced IP RTL Design Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Microarchitecture, RTL coding, Verilog, with added good understanding of SystemVerilog, UVM and Shell Scripting. Strong information technology professional with a Master of Technology (M.Tech.) focused in Electronic design from Indian Institute of Science.

Work Experience

High Tech Campus 60, Eindhoven, Noord-Brabant, 5656 AG, NL

Semiconductor Manufacturing

21724
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Saurabh Jain's Professional Milestones

  • IP Lead Engineer (2017-07-01~2022-03-01): Designing and implementing cutting-edge IP solutions, revolutionizing the field of data management and processing.
  • Asic Design Engineer (2012-03-01~2014-11-01): Developing cutting-edge artificial intelligence and machine learning algorithms to optimize user experience.
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Education

Indian Institute of Science (IISc)
Indian Institute of Science (IISc)

Electronic Design

2009-2011
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