Shiju Abraham

Professional: ------------------ - Drive early power optimization/power saving based on RTL-level power analysis using SpyGlass. Work with architects, and logic designers to understand power requirements and find opportunities to reduce power. - Report power for blocks/SubSystems and top-level using RTL-level and gate-level design and corresponding signoff tools. This is for datasheet purpose as well as for regulator sizing. Have done gate-level power reporting using RedHawk and PTPX. - Provide power projection for the future projects based on analysis, find out scaling factors between RTL, gate and Silicon. - Experience with power/IR/EM/ramp-up/ESD analysis with planar CMOS and FDSOI designs. Have worked on blocks with ~2GHz speed and also on low power SoC. - RedHawk physical and electrical modeling of Power Switches, LDOs, other IPs - CMM generation using aplmmx/Totem, Power Noise (simultaneous switching noise) analysis using Totem - Performed clock-jitter analysis using RedHawk for a high speed block. - Co-design experience. IO/Bump placement, RDL routing. - Synthesis and pre-layout timing analysis for SoC/SubSystems. - IOSTA for a few interfaces (25MHz - 133MHz). - Worked on different aspects of Physical Design(Floor Plan, Power Plan, PnR, PV) for 2 successful ASICs in 55nm technology (netlist to GDSII). - Worked on Library development for Standard Cell/IO Cells and IBIS Modeling. Academic: --------------- - MS-Thesis : Developed one of the most compact (layout area) GPIOs in 28nm technology and developed an EDA tool ("IO Planner") which help the user to plan the IO ring suitably by suggesting optimum placement for ESD clamps in the IO ring. Advisor: Dr. Alan W Davis. Personal: ------------- - Have worked and lived in India, The Netherlands and USA. Worked with global team members and tool AEs who are located at different locations/time zones. - A quick learner and a good team player. - Professional in approach, organized, result as wells as detail oriented. Goals: --------- - Explore power integrity analysis and solutions, power architecture, Synthesis, and STA.