Simple Agarwal
MTS Silicon Design Engineer@ AMD
Canada
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Simple Agarwal is an ASIC Design Automation Engineer at Intel Corporation with 11.3 years of work experience. He is skilled in Microsoft Word, C, C++, and Java, as well as programming languages like C++ and Java. Simple has worked at Intel Corporation in various roles, including Member of Technical Staff and Senior Lead Engineer. He also has experience as a Senior Engineer at Qualcomm and as a Technical Engineer at GE. Simple is based in Bengaluru, Canada.
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Emails and Phone Numbers

@qti.qualcomm.com
@gmail.com
@qualcomm.com
@intel.com
@amd.com
+1 858658****
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About

ASIC Design Automation Engineer at Intel Corporation

Work Experience

2485 Augustine Drive, Santa Clara, California, 95054, US

Semiconductor Manufacturing

29831
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Simple Agarwal's Professional Milestones

  • Asic Design Automation Engineer (2016-07-01~2018-03-01): Developing and implementing integrated AI algorithms to optimize design automation processes.
  • SOC Design Engineer (2018-04-01~2019-01-01): Implementing scalable and efficient SOCI solutions, optimizing network performance and enhancing data management.
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Education

Nirma University, Ahmedabad, Gujarat, India
Nirma University, Ahmedabad, Gujarat, India

Vlsi Design,

Masters,

Master Of Technology

2014-2016
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