Sudhir Satpathy
Computed Silicon Architect@ Facebook
Bhubaneswar, Orissa, India
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Sudhir Satpathy is a highly experienced professional with 17.5 years of work experience in the field of silicon security and data compression. He has a strong skill set in MATLAB, C, nanotechnology, engineering, and simulations. Sudhir has led technology development for silicon security and data compression, focusing on lossless data compression/decompression acceleration. He has expertise in various compression algorithms, threat modeling, security life-cycle management, and SoC security architecture specification. Sudhir has a proven track record of filing over 100 patents and publishing 50 research articles and prototyped 25 ASICs while owning security and compression subsystems.
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Emails and Phone Numbers

@intel.com
@meta.com
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About

Leads technology development for silicon security and data compression. Areas of expertise include: 1. Lossy and lossless data compression/decompression acceleration: Custom video and graphics compression algorithms, DEFLATE, Brotli, ZSTD, LZ variants, Huffman encoding, and emerging standards for real-time content processing. 2. Threat modelling, security life-cycle management, SoC security architecture specification encompassing RoT (root of trust), secure-boot, asset management, device attestation, user authentication, biometrics, privacy-preserving information processing, secure-DFT, secure-debug etc. 3. Side-channel attack resistant symmetric and public key cryptography: ECC, RSA, ECDSA, PKI, PKCS. 4. Geo-specific and light-weight cipher accelerators: SM4, SM3, AES, SHA, Camellia, Whirlpool etc. 5. Authentication and entropy extraction IPs: PUF, TRNG, crypto-currency, block-chain acceleration. Filed more than 100 patents, and published >50 research articles, prototyped 25 ASICs while owning security and compression sub-systems.

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Work Experience

Enterprise Road, Southampton, England, United Kingdom, SO16 7

Software Development

27484
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Sudhir Satpathy's Professional Milestones

  • Graduate Technical Intern (2011-04-01~2011-08-01): Developed advanced technical skills through thorough analysis and hands-on experience techniques.
  • Computed Silicon Architect (2018-11-01~): Developed advanced silicon architecture, helping optimize performance and efficiency in complex silicon projects.
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Education

University of Michigan - Rackham Graduate School
University of Michigan - Rackham Graduate School

Electrical And Electronics Engineering

2007-2010
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