Tiago Cruz

> 3 years’ experience in FPGA design – IP and SOC > 2 years’ experience in ASICs design – IP and SOC > 6 years’ experience in DFT projects - Worked on global SOC projects in global DFT project team. - Experienced in specification and implementation of DFT architecture (single and multiple power domains) - Worked in close collaboration with frontend, verification, backend and test engineering teams - Experienced in use of ATPG, generation of test patterns for SOC projects, physical and logical Scan partitions, Scan chain compression and pattern debug. - Responsible for DFT design/flow improvements (flow automatization) - Scan/JTAG/Boundary scan insertion and ATPG pattern generation - Experienced on Memory Test and Repair. MBIST logic generation, SOC integration and verification - Silicon bring-up, diagnosis and support for physical failure analysis - Worked with STA engineer to define timing constraints for DFT modes