Principal IC Design Verification@ ams AG
Plano, Texas, United States
Tieling Xie
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Mississippi State University
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FlashIntel GPTTieling Xie is an experienced mixed signal design and verification engineer with 18.4 years of work experience. He is skilled in various areas such as CMO, mixed signal, static timing analysis, and verilog. Tieling has worked at reputable companies like ams AG, Active-Semi International, TDK InvenSense, Intel Corporation, and Cypress Semiconductor Corporation. He has expertise in mixed signal simulation, debugging, and behavior modeling using SV-RNM, verilogAMS-wreal, and UVM test bench. Tieling is based in the United States.
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About
Experienced mixed signal design and verification Engineer. Skilled in mixed signal simulation, debug, verification, behavior modeling using SV-RNM, verilogAMS-wreal, UVM test bench.
Work Experience
Principal IC Design Verification
Semiconductor Manufacturing
Tieling Xie's Professional Milestones
- Cad Engineer (2005-09-01~2006-09-01): Creating flawless data visualizations for design solutions, enhancing decision-making processes for successful project implementation.
- Sr Staff Design Engineer (2014-01-01~2015-01-01): Developed new design solutions, driving creativity and accelerating business growth.
Education
Electrical Engineering,
Master Of Science,
Masters
2002-01-01-2005-01-01Skill
Cmos
Mixed Signal
Static Timing Analysis
Verilog
Dft
Primetime
Verilog Ams
Physical Design
Spectre
Timing Closure
Digital And Mix Signal Circuit Design
Integrated Circuit Design
Asic
Semiconductors
Ic
Electronics
Vlsi
Debugging
Analog
Soc
Rtl Design
Certification
Colleagues
Other Named Tieling Xie
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Tieling Xie works for ams AG
Tieling Xie's role in ams AG is Principal IC Design Verification
Tieling Xie works in the industry of Semiconductor Manufacturing
Tieling Xie's colleagues are Anthony Samuel,Bruce Ulrich,Kirk Laney
Tieling Xie's latest job experience is Principal IC Design Verification at ams AG
Tieling Xie's latest education in Mississippi State University
