Umesh Shirsalkar
senior engineer at ti@ Texas Instruments
Dallas, Texas, United States
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Umesh Shirsalkar is a highly experienced Physical Design Closure expert with 29.4 years of work experience. He possesses strong hands-on design knowledge on backend flows and implementation. Umesh is skilled in IP and SOCs and has a track record of meeting aggressive project schedules. He has extensive knowledge of VLSI design tools such as Magma, Synopsys, Cadence, MentorGraphics, Apache, and RedHawk. Umesh is known for his excellent oral, written, communication, and organizational skills, with a strong attention to detail.
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Emails and Phone Numbers

@yahoo.com
@ti.com
@ti.com
+1 407206****
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About

- Physical Design Closure expert with strong hands-on design knowledge on backend flows and implementation. - Extensive experience on IP and SOC's. - Able to meet aggressive project schedules. - Posses hands knowledge of wide range of VLSI design tools including Magma(Talus/Blast/Quartz), Synopsys (Astro/PC/dc_shell/pt_shell/STAR-RC), Cadence(FE/Nanoroute), MentorGraphics (IC Station), Apache (RedHawk). - Excellent oral, written, communication and organizational skills, with strong attention to detail.

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Work Experience

12500 TI Boulevard, Dallas, TX, 75243, US

Semiconductor Manufacturing

30287
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Umesh Shirsalkar's Professional Milestones

  • Senior Product Development Engineer (1994-05-01~2000-06-01): Driving product innovation through strategic testing and product execution.
  • senior engineer at ti (2000-06-01~): Developed innovative design solutions while driving technological advancements and delivering excellence in product excellence.
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Education

Texas A&M University-Kingsville
Texas A&M University-Kingsville

Electrical Engineering

1991-1993