Vaibhavi Rastogi

Associate Staff Engineer at Samsung Electronics, Bangalore in the SOC Design Verification, Flash Controller, Memory Solutions team. Expertise in post-netlist Gate Level Simulations, Hardware/Software Co-design/co-simulations, Interconnect verification and Flash Subsystem(FSS) RTL verification. Currently working on full-path(Host to Device) Gate Level Simulations of a SATA-based SoC. Technical Skill Set  UVM, Protocols - SAS, NVMe, AMBA - AXI, APB, AHB, Gate Level Simulations, Functional Verification, Analog and Digital Circuit Design, Static Timing Analysis  Languages - System Verilog, Verilog HDL, Python, C, MATLAB, LATEX  EDA and Verification Tools - Cadence Interconnect Workbench, Cadence Virtuoso, Cadence Indago, Cadence Simvision, Synopsis Verdi, LT-SPICE Area of interest:  SoC/IP Verification using SV/UVM.  High-Performance Computing Systems and Memory Systems  System-on-Chip design and architecture  CMOS VLSI Design  Open to learning new technologies and working in novel areas related to VLSI System Design and Computer Architecture.