Vipula Sateesh
Senior FPGA Design Engineer@ Tarana Wireless, Inc.
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Vipula Sateesh is a Senior Fpga Design Engineer with 6.7 years of experience. She is based in the United States and has worked at Tarana Wireless, Inc. in California as a Senior Fpga Design Engineer. She also has experience as a Machine Learning Engineer at Sapient Industries in Pennsylvania. Vipula has expertise in telecommunications, information and cultural products, and software development.
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Research Details
Skills & Insights
Colleagues

Emails and Phone Numbers

@taranawireless.com
@taranawireless.com
@sapient.industries
+1 408351****
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Work Experience

590 Alder Dr, Milpitas, California, 95035, US

Telecommunications

410
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Vipula Sateesh's Professional Milestones

  • Machine Learning Engineer (2017-01-01~): Optimized machine learning processes, enabling efficient and accurate decision-making within the organization.
  • Senior FPGA Design Engineer (2022-08-01~): Successfully implemented and optimized spatial planning systems for new complex engineering projects.

Education

University of Pennsylvania
University of Pennsylvania

Electrical And Electronics Engineering

1483228800-1546300800
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