senior design engineer at microsoft@ Microsoft
Raleigh, North Carolina, United States
Viren Patel
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North Carolina State University
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FlashIntel GPTViren Patel is a dedicated and highly motivated Hardware Design Engineer with 14 years of experience in CPU/L2 microarchitecture and Logic design. He has expertise in systemverilog, timing closure, RTL design, logic design, and formal verification. Viren has worked for companies like Microsoft and Qualcomm, where he held positions as a Senior Design Engineer and Staff Design Engineer. He is skilled in code and functional coverage analysis, design-for-test, synthesizing, timing closure, and formal Equivalence Validation. Viren is currently based in the United States.
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Dedicated and highly motivated Hardware Design Engineer with 14 years of experience in CPU/L2 microarchitecture, Logic design and verification using Verilog/SystemVerilog, Code and Functional Coverage Analysis, Design-for-Test, Synthesis, Timing Closure, Formal Equivalence Validation and collaborative project deliveries for many market-place successful, high-performance, low-power custom Arm based processors for Qualcomm server and mobile solutions, commercialized as Centriq and Snapdragon chipsets respectively.
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senior design engineer at microsoft
Software Development
Viren Patel's Professional Milestones
- Staff Design Engineer (2004-06-01~2019-02-01): Creating innovative and user-friendly designs to enhance product functionality and optimize performance.
- senior design engineer at microsoft (2019-02-01~): Designing innovative and high-quality engineering solutions to streamline project efficiency and exceed quality standards.
Education
Computer Engineering,
Master Of Science,
Masters,
Electrical And Computer Engineering
2003-2005Skill
Systemverilog
Timing Closure
Rtl Design
Logic Design
Formal Verification
Dft
Hardware Verification
Coverage Analysis
Arm Architecture
Hardware Architecture
Debugging
Application Specific Integrated Circuits
System On A Chip
Verilog
Perl
Cpu/l2 Cache Design
Processors
Functional Verification
Logic Synthesis
Primetime
Certification
Colleagues
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Viren Patel works for Microsoft
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