Yash Patel
asic design at amd@ AMD
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Yash Patel is an experienced Asic Design Engineer with 8.6 years of work experience. He is skilled in various areas such as ASIC/FPGA development flow, VLSI design, physical design, and Logic design. Yash has expertise in languages like Verilog, SystemVerilog, C, C, Perl, and Tcl. He has worked at Ayar Labs, Axiado Corporation, The University of Texas at Dallas, and Cognizant. Yash has also gained experience as a Teaching Faculty and a Programmer Analyst Trainee. He is currently based in the United States.
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Emails and Phone Numbers

@amd.com
+1 408749****
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About

Good knowledge and experience in ASIC/FPGA development flow, VLSI design, Physical Design (RTL to GDSII), Static Timing Analysis (STA), Digital Design, SOC, Logic design, Synthesis, Validation, Scripting, Low Area, Low Power, Place and Route (P&R), SignOff, and Computer Architecture. Strengths: Languages: Verilog, SystemVerilog, C, C++, Perl, Tcl. Tools: Cadence (Virtuoso Layout Suite, Schematic Editor, Encounter), Xilinx (ISE, Vivado, SDK, ISIM), Synopsys (Design Vision, IC Compiler, IC Compiler II, Formality, StarRC, IC Validator, SiliconSmart ACE, Primetime, TetraMax, VCS), HSPICE, Waveview, ModelSim SE, Code composer studio(TI), Eclipse IDE, MatLab, Ansys RedHawk. Devices: Xilinx Zybo 7000, Xilinx Ultrascale (XCVU 440).

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Work Experience

2485 Augustine Drive, Santa Clara, California, 95054, US

Semiconductor Manufacturing

29831
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Yash Patel's Professional Milestones

  • ASIC Design Engineer (2020-11-01~): Creating innovative and efficient design solutions for complex engineering projects.
  • Teaching Faculty (2015-07-01~2016-06-01): Elevated student academic excellence through effective supervision and teaching strategies.
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Education

The University of Texas at Dallas
The University of Texas at Dallas

Electrical And Electronics Engineering (circuits And Systems Group)

2016-2018
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