Yichen Zhao
sr fpga prototyping engineer at spreadtrum@ Spreadtrum
Shanghai, Shanghai, China
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Yichen Zhao is a highly skilled professional with 14.4 years of experience in various fields such as verilog, matlab, fpga, python, and chipscope. Based in Shanghai, China, Yichen holds an M.S. Candidate degree in Electrical Engineering and Computer Science at Oregon State University, Corvallis, USA. With expertise in wireless and TCP/IP protocol, Yichen is proficient in FPGA-based design and has strong knowledge in digital design and RTL synthesis. Yichen also has experience in interfacing FPGAs to DDS clocking modules and AD/DA converters.
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Emails and Phone Numbers

@spreadtrum.com
@gmail.com
@unisoc.com
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About

M.S. Candidate in the School of Electrical Engineering and Computer Science at the Oregon State University, Corvallis, USA. Specialties: My research include Familiar with WLAN and TCP/IP protocol Familiar with Python Experience and strong fundamentals in FPGA based design: designed, analyzed, simulated and built FPGA based systems Excellent Verilog coding and Matlab simulation Strong knowledge in digital design and RTL synthesis, test bench design, simulation Fluent lab test experience Experience interfacing FPGAs to DDS clocking modules and AD/DA converters

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Work Experience

Building No. 1, Shanghai, 201203, CN

Semiconductor Manufacturing

1274

Yichen Zhao's Professional Milestones

  • sr fpga prototyping engineer at spreadtrum (2013-09-01~): Enhanced prototype design by implementing innovative solutions, driving development and success.
  • Fpga Prototyping Engineer (2013-09-01~): Creating cutting-edge prototypes with precision and creativity, revolutionizing the real world.

Education

Oregon State University
Oregon State University

Electronics,

Engineering,

Communications,

Master Of Science,

Masters,

Electrical,

Electronics And Communications Engineering

1262304000-1356998400