Yves Dubois
Lead Physical Design Engineer@ Eviden
Paris, Île-de-france, France
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Yves Dubois is an experienced Asic Physical Design Engineer with over 20 years of work experience. He has a strong skill set in various areas such as fpga, fpga, soc, ii, verilog, vhdl, dft, rtl design, static timing analysis, pcie, microcontrollers, p&r, formal proof, timing closure, power analysis, signal integrity, physical verification, and logic synthesis. Yves has worked at reputable companies like Atos, MELEXIS, Bull, Thales, Nokia, and Xerox, gaining expertise in the field of semiconductor manufacturing and digital design.
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Emails and Phone Numbers

@comcast.net
@eviden.com
@atos.net
@comcast.net
@melexis.com
@elsys-design.com
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Work Experience

Bezons, FRANCE, 95870, FR
18063
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Yves Dubois's Professional Milestones

  • ASIC Physical Design Engineer (2019-05-01~): Designing cutting-edge designs, elevating design standards for maximum performance and efficiency.
  • Fpga Design Engineer (2010-06-01~2010-08-01): Developed innovative FGGA applications to streamline production processes and streamline operational processes.
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