Zhenhua Zhu John

Technical Experience Summary: 4G/5G modem transmitter AFE and Phase interpolator design and optimization experience Comprehensive circuit design experience in SoC low power PLLs design, testing, debugging and optimization Designed three generations of PLLs used in multiple Intel Atom processors, including core CPU processor PLL, display PLL, generic PLL. Extensive teamwork experience with worldwide design centers. Comprehensive knowledge in microprocessor clocking architecture choices and design tradeoffs. In-depth knowledge of semiconductor devices. Experience: 2009.01 – present Intel Corp. Senior Analog/Mixed Signal Design Engineer 8GHz/12GHz Phase Interpolator Design and Optimization. Transmitter AFE design owner responsible for an 8GHz Transmitter in DigRF Modem. PLL IP owner and lead designer responsible for overall PLL performance optimization Designed low power PLL for DigRF Modem. Provided PLL IPs for Intel Atom cellphone/tablet processor. Designed core PLL/display PLL/generic PLL in Intel 14nm technology. PLL output frequency ranges from 80MHz to 3800MHz. Designed USB PLL/DISPLL in Intel 20nm Technology with five stage differential VCO up to 3.5 GHz. Design and implementation of custom macros in both input and output drivers and receivers and core Phase-Lock-Loops (PLL), including amplifier design, charge pumps, voltage-controlled oscillators tuning, voltage regulators. Education: 2005.8-2008.9 Lund University, Lund, Sweden MSEE in System-On-Chip (mixed signal IC design track) Thesis: CMOS circuits design of a low power and area efficient USB transceiver. Current Status: Canadian citizen, US Green Card