Harsh Mehta
IC Design Engineer | Chip Power Integrity@ Broadcom
Austin, Texas, United States
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Harsh Mehta is an experienced professional with 14.7 years of work experience in various fields such as Verilog, Asic, debugging, Perl, simulations, TCL, and computer architecture. He holds a MS in Electrical Engineering with a focus on Digital & Computer Engineering. Harsh has a strong understanding of CAD tools, digital systems architecture, and Logic Design, with a deep understanding of FPGA & ASIC design flow. He has worked as a Lead Product Engineer at Cadence Design Systems and as a Power and Reliability Cae at Synopsys Inc. Harsh has also gained experience as an Instructional Student Assistant at California State University, Northridge, and as
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Emails and Phone Numbers

@brocade.com
@cadence.com
@synopsys.com
@yahoo.com
+1 408943****
+1 949926****
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About

* MS in Electrical Engineering with emphasis on Digital & Computer Engineering. * Understanding of CAD tools for design / Simulation / Synthesis. * Knowledge of Digital systems architecture and Logic Design with understanding of FPGA & ASIC design flow. * knowledge of Hardware Components, Schematics and Layouts

Work Experience

1320 Ridder Park Drive, San Jose, California, 95131, US

Semiconductor Manufacturing

56738
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Harsh Mehta's Professional Milestones

  • Instructional Student Assistant (2010-08-01~2012-05-01): Assisting students in school by providing exceptional support and educational support.
  • Intern , Solution Group (2012-05-01~2012-10-01): Successfully supervised and managed business operations, collaborating with cross-functional teams for seamless execution of projects.
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Education

Gujarat University
Gujarat University

Communication,

Electronics,

Bachelors,

Bachelor Of Science

2005-2009