Jatin Nagpal
Senior Design Verification Engineer@ Analog Devices
Gautam Buddha Nagar, Uttar Pradesh, India
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Jatin Nagpal is a highly skilled professional with 12.3 years of experience in various programming languages and technologies such as Verilog, System Verilog, VLSI, C, and more. Currently, he is working on Transactor development for the Emulation Platform. He has previously worked on product validation and quality monitoring for Synopsys software tool VCS. Jatin has also gained valuable experience as an intern at Mentor Graphics. He is based in India and has a strong background in digital electronics and data structures.
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Emails and Phone Numbers

@mentor.com
@gmail.com
@synopsys.com
@aol.com
+1 919547****
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About

Presently i am working on Transactor development for Emulation Platform.It requires RTL and C development.Previously , I was working in product validation and Quality monitoring of synopsys software tool VCS . The priciple responsibilities includes validation and quality monitoring of the tools for various HDL's/HVL's (verilog/System, Verilog) and UVM.

Work Experience

One Analog Way, Wilmington, MA, 01887, US

Semiconductor Manufacturing

23214
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Jatin Nagpal's Professional Milestones

  • Intern (2011-06-01~2011-07-01): Contributed to the research, writing, and analysis of high-impact articles, contributing to the advancement of knowledge
  • Senior R & Director Engineer (2017-10-01~): Driving engineering excellence and innovation through strategic planning and execution.
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